The invention relates to a latch circuit, and more particularly to a latch circuit suitable for high-speed operation at low supply voltages.
Latch circuits are commonly used circuits, e.g., for memorizing a binary signal, for use in state machines, frequency dividers, counters. Modern technology trends are low-voltage supply for digital circuits for obtaining a relatively lower power consumption of logic families operating at lower and lower supply voltages and down-scaling of the oxide thickness for reliability reasons. When speed is an important feature, the design of digital building blocks may be inspired by analog techniques since any of the classical digital solutions working at low speed do not provide the required performance. The fastest logic family is MOS technology, which is widespread in modern integrated circuits, is the so-called Source Coupled Logic (SCL) family. However, at relatively low supply voltages, e.g., 1.2 V or lower, SCL family does not work properly due to the stacking of transistors, i.e., between a positive supply voltage and ground there are at least three transistors. This category includes AND, OR, XOR gates and the D-latch. The D-latch is relatively difficult function to be implemented because the requirements for a relatively small set-up and hold times are obtained with a relatively high power consumption. When working with signals having a period comparable with the time delay through the latch, the latch requires high gain to operate correctly. However, the transconductance of modern MOS transistors is lower than their bipolar counterparts and therefore larger transistors and higher currents are necessary. As a consequence, the rise and fall times of the digital signals are deteriorated and therefore the operating speed of the circuit is reduced.
U.S.-2003/0001646 describes, among other circuits, a latch circuit as shown in FIG. 6. FIG. 6 shows an SCL triggered D-latch. When CK is positive, the differential pair M1, M2 tracks the input D and on the negative level of the CK the latch M3, M4 becomes active memorizing in a binary format the input signal provided at the D input. This circuit has several disadvantages.
The supply voltage is limited to VGS+2(VGS−VT)+ΔV, where VGS is the gate-source voltage of one of the transistors M1 . . . M4, or the MOS current source I0, VT is the threshold voltage of the transistors and ΔV is the voltage drop on the resistor R needed to bias the transistors M1 and M2. In modern processes like CMOS18 the supply voltage is limited to 1.8 V and the circuit should work at 1.62 V (1.8 V-10%).
The latch and the differential pair share the same load together. Therefore the latch has the difficult task to take decisions on a large capacitance load given by its own stray capacitances the parasitic capacitances of M1 and M2 and the load capacitance given by wiring, fan-in and the resistor R. The use of a buffer between the latch and the gain stage is excluded due to the lack of voltage headroom and the lack of good source-followers in baseline digital processes.
The intrinsic delay between the data path and the clock path. The clock path has a larger delay than the data path and therefore the delay times from CK to Q output (tdCK−>Q) and from D to Q output (tdD−>Q) are not equal . This can impair the function of a phase detector and can generate extra offset in a PLL loop in lock.
The transistors are stacked. Thus the operating level of the Δ and CK signals are different. Level shifting between the D levels and the CK level, needs extra source followers or other level shifters that decrease the speed of operation and increase the delay between the data path and the clock path.
Hence, there is a need to obtain a latch operating at relatively high frequency and using relatively low supply voltages.